1. Field of the Invention
The invention relates in general to a signal calibration apparatus, and more particularly to a signal calibration apparatus for use in a charge pump.
2. Description of the Related Art
Phase locked loop (PLL) is a circuit for controlling the frequency and the phase of its output signal according to a criterion. Nowadays, the achievement of a high-speed, low-noise PLL is the major subject to be devoted to.
FIG. 1 illustrates the block diagram of a PLL 100 according to a traditional method. The PLL 100 includes a phase/frequency detector (PFD) 102, a loop filter (LP) 104, a voltage controlled oscillator (VCO) 106, and a frequency divider (FD) The PFD 102 receives an input frequency fIF and a reference frequency fref, and then outputs a signal S1 to the LP 104 according to the phase difference between the input frequency fIF and the reference frequency fref. The LP 104 filters out the noise and then outputs a signal S2 to the VCO 106. The VCO 106 outputs an output frequency fOF, which is also the output signal of the PLL 100 and is fed back to the FD 108. The FD 108 outputs the reference frequency fref, which is equal to the output frequency fOF divided by a positive integer N, wherein the positive integer N is determined by a control signal fCO.
After a settle time from the starting of the PLL 100, the PLL 100 goes to a lock state, wherein the reference frequency fref is equal to the input frequency fIF, and the output frequency fOF is equal to the positive multiple of the input frequency fIF.
Please refer to FIG. 2; it shows a charge pump 200, which is the post-stage of the PFD 102. The charge pump 200 has a current source IUP and a current source IDN for respectively receiving a rising signal fup and a descending signal fdn from the pre-stage, wherein the rising signal fup and the descending signal fdn are determined according to the phase difference between the reference frequency fref and the input frequency fIF. The current source IUP outputs current iup according to the rising signal fup while the current source IDN outputs current idn according to the descending signal fdn. Hence, the current iup and current idn relate to the phase difference between the reference frequency fref and the input frequency fIF. The charge pump 200 outputs a current IO, which is the difference between the current iup and current idn and is proportional to the phase difference between the reference frequency fref and the input frequency fIF.
Ideally, the characteristics of the current sources IUP and IDN are identical. When they receive the same signals, the current iup outputted from the power source IUP is equal to the current idn outputted from the current source IDN, and thus the current IO is zero. However, such the circuit elements of the same kind as the two current sources, in reality, have slight variations in physical characteristic. Thus, the current iup outputted from the current source IUP will not be equal to the current idn outputted from the current source IDN when the current source IUP and the current source IDN respectively receive the rising signal fup and the descending signal fdn in the same magnitude. In this case, the output current IO will not be zero even if the reference frequency fref and the input frequency fIF are in phase, thus degrading the performance of the PLL in phase-locking. Therefore, it is desirable to have a charge pump with higher precision to overcome these limitations to the PLL.